1. Field of the Invention
The present disclosure relates to the field of switching in a Clos network. Specifically, the present disclosure relates to a universal element that can dynamically change its role for various stages.
2. Description of Related Art
Clos and folded Clos packet switching network architectures are widely used in high performance computing clusters and big scalable routers. The simplest full Clos architecture requires 3-stage switching and 3 types of switching fabrics. For the folded Clos, the simplest form uses 3 stages and 2 types of fabrics.
Usually, a 3-stage Clos network is described with 3 distinct parameters: n, k, and m, where n is the number of egress links per each of the stage 1 and stage 3 nodes, k is the number of stage 2 nodes, and m is the number of stage 1 or stage 3 nodes. A first set of ingress links connect each stage 1 node to each stage 2 node, and a second set of ingress links connects each stage 2 node to each stage 3 node. Because of the connectivity, the number of stage 2 nodes, k, is equal to the number of ingress links, and the number of stage 1 or stage 3 nodes is equal to the number of ingress links per each stage 2 node. The size of a network, or the total number of egress links, is N=n×m.
A Clos network has an expansion factor of E=k/n. The expansion factor is a measure of data flow in a network. Typically, a Clos network can be non-blocking when m≧2n−1. This non-blocking characteristic may be crucial for networks with burst traffic and traffic composed of fractions of multicast packets.
Developing an “on the chip” solution, or having all components on one chip, for high performance switching elements suffers from a number of physical limitations. The limitations include essential power dissipation, form-factor limitations for high bitrate electronic Serializers/Deserializers (SerDes'es) as the number of elements increases, distances between the elements, and interconnection complexity when using switching fabrics with a low capacity. A Clos network with low capacity switches requires more stages and thus more switching elements and physical connectors to be placed on a chip.